Keysight Technologies PathWave ADS 2023 automates workflows from design to test


Keysight Technologies launched PathWave Advanced Design System (ADS) 2023 for high-speed digital design (HSD) with new memory design capabilities for modeling and simulating next-generation interface standards such as Double Data Rate 5 (DDR5).

As data center throughput increases, expectations for server and high-performance computing performance drive the need for new ultra-fast high-density memory or DDR5 dynamic random-access memory (DRAM).

Operating at twice the data rate of DDR4 memory results in reduced design margins and makes it difficult for hardware designers to optimize printed circuit boards (PCBs) to minimize reflection, crosstalk and of jitter.

Additionally, lower voltages, higher currents, and new equalization requirements in the DRAM receiver create signal integrity issues that are difficult and costly to resolve.

Keysight’s PathWave ADS 2023 for HSD ensures fast simulation setup and advanced measurements while providing designers with essential information to overcome signal integrity challenges.

Its new memory designer builds parameterized memory buses using the new pre-layout constructor, allowing designers to explore system tradeoffs that reduce design time and reduce product development risk for DDR5, Low -Power Double Data Rate (LPDDR5/5x), and Graphics Double Data Rate (GDDR6/7) memory systems.

“The biggest advantage of our first DDR5 design is the number of aspects to consider with the simulation,” said Lorenzo Forni, PCB and SI/PI design manager at SECO, an Italian industry group that designs and produces embedded systems and IoT solutions.

“You have to combine stack-up analysis, routing geometry and AMI models. Luckily, we used Keysight’s Memory Designer for the DDR5 simulation and it’s very automated. The configurations are integrated and it is very simple. Setting up the Memory Designer schematic reduced the time needed and the simulation ran into a lot of issues during our design process,” Forni continued.

“Keysight has a long history of being at the forefront of channel simulation technology as well as test leadership in memory industry standards bodies, including JEDEC,” said Stephen Slater, director of PathWave HSD product management at Keysight Technologies.

“We are committed to building the broadest portfolio of products and services for DDR enablement, including a complete design-to-test workflow for DDR5 memory, from simulation to test and fix. As a result, our HSD design customers benefit from a more predictive flow and greater confidence during design approval,” continued Slater.

Key customer benefits of Keysight PathWave ADS 2023 include:

Accurate simulation and modeling

  • Supports a wide range of next-gen standards: LPDDR4, LPDDR5, GDDR6, GDDR7, HBM2/2E, HBM3 and NAND
  • Accurately predicts Data Eye closure and equalization: Minimizes the impact of jitter, ISI, and crosstalk using buffer information specification algorithmic modeling interface modeling single-ended I/O (input-output) (IBIS-AMI) with transmitted timing, DDR bus simulation, and precise electromagnetic (EM) extraction from PCB signal routing
  • Reduces time-to-market with a unique design environment that helps orient pre-silicon digital twins to meet today’s integration requirements such as transmitted timing and timing, interface modeling of IBIS Algorithmic Modeling (IBIS-AMI) and compliance testing and future challenges such as Pulse Amplitude Modulation 4 Levels (PAM4), for exploration of DDR6

Fast simulation times

  • Quickly generates busses via a parameterized pre-layout builder that allows designers to quickly generate large memory signal busses and easily create flexible layouts to explore trade-offs
  • Simulate up to 80% faster: Cloud-based high-performance computing (HPC) uses parallel processing to accelerate Memory Designer and EM simulation run times

Link simulation to test

  • Automates design-to-test workflows with easy connection between simulation and measurement domains to enable comparison of stored data with measured results from physical prototypes


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